User Manual

42
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
10.10.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator
or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be
disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to
”Internal Voltage Reference” on page 49 for details on the start-up time.
10.10.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to ”Watchdog Timer” on page 50 for details on
how to configure the Watchdog Timer.
10.10.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then
to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
I/O
) and the ADC clock
(clk
ADC
) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it
will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 80 for details on which
pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level
close to V
CC
/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC
/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on
page 241 and ”DIDR0 – Digital Input Disable Register 0” on page 257 for details.
10.10.7 On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock source
is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the
total current consumption.