User Manual

47
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
8271E–AVR–07/2012
Figure 11-1. Reset Logic
11.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”Sys-
tem and Reset Characteristics” on page 310. The POR is activated whenever V
CC
is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V
CC
rise.
The RESET signal is activated again, without any delay, when V
CC
decreases below the detection level.
Figure 11-2. MCU Start-up, RESET
Tied to V
CC
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA B U S
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
RSTDISBL
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC