User Manual

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

8271E–AVR–07/2012

11.9 Register Description

11.9.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

• Bit 7:4: Reserved

These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.

• Bit 3 – WDRF: Watchdog System Reset Flag

This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero

to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the

flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as

early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can

be found by examining the Reset Flags.

11.9.2 WDTCSR – Watchdog Timer Control Register

• Bit 7 – WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.

WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is

cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Inter-

rupt is executed.

• Bit 6 – WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE

is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding inter-

rupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and

System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt

vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is

useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset

Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine

Bit 76543210

0x34 (0x54) ––––WDRFBORFEXTRFPORFMCUSR

Read/Write RRRRR/WR/WR/WR/W

Initial Value0000 See Bit Description

Bit 76543210

(0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X 0 0 0