User Manual

ManualsBrandsSeeed Studio ManualsDevelopment Boards & KitsSeeeduino Cortex-M0+ Development Board

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

8271E–AVR–07/2012

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of

each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

Table 12-7 on page 66 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST

and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and reg-

ular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application

section while the Interrupt Vectors are in the Boot section or vice versa.

Note: 1. The Boot Reset Address is shown in Table 27-7 on page 280. For the BOOTRST Fuse “1” means unprogrammed

while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328/328P is:

Address Labels Code Comments

0x0000 jmp RESET ; Reset Handler

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp EXT_INT1 ; IRQ1 Handler

0x0006 jmp PCINT0 ; PCINT0 Handler

0x0008 jmp PCINT1 ; PCINT1 Handler

0x000A jmp PCINT2 ; PCINT2 Handler

0x000C jmp WDT ; Watchdog Timer Handler

0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler

0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler

0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler

0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler

0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler

0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler

0x001A jmp TIM1_OVF ; Timer1 Overflow Handler

0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler

0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler

0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler

0x0022 jmp SPI_STC ; SPI Transfer Complete Handler

0x0024 jmp USART_RXC ; USART, RX Complete Handler

0x0026 jmp USART_UDRE ; USART, UDR Empty Handler

0x0028 jmp USART_TXC ; USART, TX Complete Handler

0x002A jmp ADC ; ADC Conversion Complete Handler

0x002C jmp EE_RDY ; EEPROM Ready Handler

0x002E jmp ANA_COMP ; Analog Comparator Handler

0x0030 jmp TWI ; 2-wire Serial Interface Handler

0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x0033RESET: ldi r16, high(RAMEND); Main program start

0x0034 out SPH,r16 ; Set Stack Pointer to top of RAM

Table 12-7. Reset and Interrupt Vectors Placement in ATmega328 and ATmega328P

(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x000 0x002

1 1 0x000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x002

0 1 Boot Reset Address Boot Reset Address + 0x0002