Bumblebee Processor Core Concise Data Sheet
revise history versio n number Revision date Revised chapter 1.
table of Contents revise history ...................................................................................... 0 Picture list ........................................................................................................................................................................................... 4 1. Bumblebee kernel overview ............................................................................................................................................................
Picture list Figure 1-1 Top view of the bumblebee kernel ........................................................... 6 Figure 2-1 Schematic diagram of the bumblebee kernel clock domain ....................................
1. Bumblebee kernel overview The Bumblebee Processor Core, or Bumblebee core, is a commercial custom made by Nuclei System Technology in conjunction with Gigadevice for its general purpose MCU products for IoT or other ultra-low power scenarios. RISC-V processor core. Note: The Bumblebee core used for this MCU is jointly developed by Nuclei System Technology and Taiwanese Andes Technology, and Nuclei System Technology provides authorization and technical support services.
Supports 32-bit wide Instruction Local Memory (ILM) bus interface (supports standard AHBLite or SRAM interface protocols) for connecting private instruction local memory. Supports 32-bit wide Data Local Memory (DLM) bus interface (supports standard AHB-Lite or SRAM interface protocols) for connecting private data local memory.
Supports 32-bit wide Private Peripheral Interface (PPI) and supports standard APB Interface protocol for connecting private peripherals. Debugging function Support for standard jtag interfaces. Support for the risc-v debugging standard. Support for 4 hardware breakpoints (Hardware Breakpoints). Support for sophisticated interactive debugging tools. Low power management Supports WFI (Wait For Interrupt) and WFE (Wait For Event) to enter sleep mode.
1.2. Bumblebee kernel instruction set and architecture See the Bumblebee Kernel Instruction Architecture Handbook for details on the instruction set and architecture supported by the Bumblebee kernel.
1.3. Bumblebee kernel hierarchy diagram The top of the Bumblebee kernelFigure 1-1 Shown.The organizational structure of the Bumblebee kernel mainly includes the following points: Core is the top level of the entire processor core. uCore is under the Core hierarchy and is the main part of the processor core. In addition to uCore, the following main components are included under the Core hierarchy: Debug: Handles the jtag interface and related debugging features.
Figure 1-1 Top view of the Bumblebee kernel Page 14
2. Introduction to Bumblebee Kernel Features Bumblebee kernel clock domain introduction 2.1. Bumblebee kernel clockDomain division shown in Figure 2-1 As shown, the entire processor core is divided into two clock domains that are asynchronous to each other: The working clock domain, driven by the input clocks core_clk and core_clk_aon, functions most of the processor core.note: Core_clk and core_clk_aon are co-frequency, in-phase clocks from the same clock source.
Figure 2-1 Bumblebee kernel clock domain diagram 2.2.
The Bumblebee kernel does not have a power domain inside, and SoC system integrators can divide the power domain and cross-power domain processing according to the Bumblebee kernel hierarchy. 2.3. Introduction to the Bumblebee Kernel Interface The Bumblebee kernel contains the following types of interfaces: Clock and reset interface Debug interface External interrupt interface Bus interface, including the following interfaces: ILM Master Interface: An interface to access an external ILM.
Privilege Modes. 2.6.
The Bumblebee kernel supports the following types of memory resources: ILM: The Bumblebee kernel supports ILM access via a proprietary AHB-Lite bus or SRAM interface if an Instructon Local Memory (ILM) interface is configured. The size of ilm can be configured.The ilm interface has independent address ranges. You can configure the specific base address. See section 2.4 Learn more about it.
Debug: Handles the jtag interface and related debugging features. Eclic: Kernel interrupt control unit. Timer: The kernel private timer unit.
The above devices belong to the processor core and are accessed by using the memory address addressing mode. For details on the specific address range allocation, see the 2.4 Section. 2.8. Physical storage protection for the Bumblebee kernel Since the Bumblebee core is a low-power core for the microcontroller domain, it does not support virtual address management units. (Memory Management Unit), so all address access operations are physical addresses used.
For a detailed description of the Bumblebee kernel's interrupt and exception mechanisms, see the Bumblebee Kernel Instruction Architecture Handbook. 2.11. NMI mechanism of the Bumblebee kernel NMI (Non-Maskable Interrupt) is a special input signal of the processor core, often used to indicate the system layer.
Emergency errors (such as external hardware failures, etc.).After encountering the NMI, the processor core should immediately abort execution of the current program and instead process the NMI error.For a detailed description of the NMI mechanism of the Bumblebee kernel, see the Bumblebee Kernel Instruction Architecture Handbook. 2.12. Bumblebee kernel CSR register Some control and status registers (CSRs) are defined in the RISC-V architecture to configure or log the status of some operations.
The CSR register minstret reflects the lower 32 bits of the counter, and the CSR register minstreth reflects the 32-bit high value of the counter.See the Bumblebee Kernel Instruction Architecture Handbook for more information on minstret and minstreth. The Clock Counter and the Instruction Retirement Counter are typically used to measure performance.
By default, the counter has a value of 0 after a kernel reset and then continues to increment itself.Since the counter count consumes some dynamic power consumption, in the implementation of the Bumblebee kernel, a number of additional control fields are added to the custom CSR register mcountinhibit. The software can configure the corresponding control fields to separate the different counters. Stop, so stop counting when you don't need to use them to save power.
the debugger's functionality.If the timer still counts while executing the code set by these debuggers, it does not truly reflect the true debugged.Therefore, code set by the behavior when debugger, the the of the Bumblebee timer program kernel will being executes automatically the stop counting. 2.14.2. Timer behavior in normal mode By default, the timer has a value of 0 after a kernel reset and then continues to increment itself.
Stop counting to achieve power saving.See the Bumblebee Kernel Instruction Architecture Manual for details on the CSR register mcountinhibit. 2.15. Low-power mechanism of the Bumblebee core The low-power mechanism of the Bumblebee core is reflected in the following aspects: The clocks of the main units inside the Bumblebee core are automatically gated off when idle to save static power.
2.15.2. Clock control to exit sleep The processor core can be interrupted, interrupted, or NMI awake. See the Bumblebee Kernel Instruction Architecture Manual for details on how to exit hibernate.
The key points of clock control when the processor core exits the sleep state are as follows: If the wakeup is waiting for an interrupt, the interrupt of the Bumblebee core needs to be processed and distributed by the ECLIC unit. The interrupt can only wake up the kernel after passing the conditions such as the enable and priority thresholds.In addition, pay special attention to whether the processor core's normally open clock (core_clk_aon) is off: Such as the first 2.
The output signal core_wfi_mode is pulled low immediately after the processor wakes up.Assume that the SoC system level is used. Core_wfi_mode controls the core's core_clk gated clock, and as the core_wfi_mode signal is pulled low, the processor core's working clock core_clk will be reopened.