User Manual

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2. Introduction to Bumblebee Kernel Features
2.1. Bumblebee kernel clock domain introduction
Bumblebee kernel clockDomain division shown in Figure 2-1 As shown, the entire
processor core is divided into two clock domains that are asynchronous to each other:
 The working clock domain, driven by the input clocks core_clk and core_clk_aon,
functions most of the processor core.note:
 Core_clk and core_clk_aon are co-frequency, in-phase clocks from the same
clock source.
 Core_clk is the main operating clock that drives the main working logic
inside the processor core and can be globally gated at the system level.
 Core_clk_aon is a normally open clock that drives the Always-On logic in the
core, mainly including ECLIC.
TIMER and DEBUG.See the Bumblebee Kernel Instruction Architecture
Handbook for more information on ECLIC and TIMER.
 The JTAG clock domain, driven by the input signal jtag_TCK, drives the JTAG
debug-related logic of the processor core.
The above two clock domains are completely asynchronous, and asynchronous cross-clock
domain processing has been performed in the internal implementation of the processor
core.