User Manual

Page 14
Emergency errors (such as external hardware failures, etc.).After encountering the NMI,
the processor core should immediately abort execution of the current program and instead
process the NMI error.For a detailed description of the NMI mechanism of the Bumblebee
kernel, see the Bumblebee Kernel Instruction Architecture Handbook.
2.12. Bumblebee kernel CSR register
Some control and status registers (CSRs) are defined in the RISC-V architecture
to configure or log the status of some operations.The CSR register is a register
internal to the processor core and uses its proprietary 12-bit address encoding
space.See the Bumblebee Kernel Instruction Architecture Handbook for details.
2.13. Performance counters for the Bumblebee kernel
The risc-v architecture defines the following two performance counters:
Clock Counter:
A 64-bit wide clock cycle counter that reflects how many clock cycles the processor has
executed.This counter continuously increments as long as the processor is in the
execution state.
The CSR register mcycle reflects the lower 32 bits of the counter, and the
CSR register mcycleh register reflects the 32-bit high value of the
counter.See the Bumblebee Kernel Instruction Architecture Handbook for more
information on mcycle and mcycleh.
Instruction Retirement Counter:
The risc-v architecture defines a 64-bit wide instruction completion
counter that reflects how many instructions the processor successfully
executed.This counter increments as long as the processor completes an
instruction every successful execution.