User Manual

Page 14
By default, the counter has a value of 0 after a kernel reset and then continues to
increment itself.Since the counter count consumes some dynamic power consumption, in the
implementation of the Bumblebee kernel, a number of additional control fields are added
to the custom CSR register mcountinhibit. The software can configure the corresponding
control fields to separate the different counters. Stop, so stop counting when you don't
need to use them to save power.
See the Bumblebee Kernel Instruction Architecture Manual for details on the CSR
register mcountinhibit.
2.14. Timer unit of the Bumblebee kernel
The RISC-V architecture defines a 64-bit Timer Counter that is clocked by the
system's low-speed Real Time Clock frequency.The value of this timer is reflected in
the mtime register in real time.The RISC-V architecture also defines a 64-bit
mtimecmp register that serves as a comparison value for the timer. A timer interrupt
is generated assuming that the value mtime of the timer is greater than or equal to
the value of mtimecmp.
Note: The RISC-V architecture does not define the mtime and mtimecmp registers as
CSR registers, but rather as system registers for Memory Address Mapped. The specific
memory mapped address RISC-V architecture is not specified, but is instead The kernel
designer implements it on its own.In the implementation of the Bumblebee kernel,
mtime/mtimecmp is
TIMER unit implementation, see the Bumblebee Kernel Instruction Architecture Handbook
for details on the TIBR unit of the Bumblebee kernel.
2.14.1. Timer behavior when debugging mode
W h e n t h e B u m b l e b e e k e r n e l i s i n d e b u g m o d e , i t
o c c a s i o n a l l y e x e c u t e s s o m e d e b u g g e r ( D e b u g g e r ) s e t c o d e ( i n
t h e D E B U G u n i t , w h i c h i s i n v i s i b l e t o t h e u s e r ) t o s u p p o r t