User Manual

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Stop counting to achieve power saving.See the Bumblebee Kernel Instruction Architecture
Manual for details on the CSR register mcountinhibit.
2.15. Low-power mechanism of the Bumblebee core
The low-power mechanism of the Bumblebee core is reflected in the following aspects:
The clocks of the main units inside the Bumblebee core are automatically
gated off when idle to save static power.
The Bumblebee kernel supports Sleep mode through common WFI (Wait for
Interrupt) and WFE (Wait for Event) mechanisms for low dynamic and static
power consumption. For "Wait for Interrupt" and "Wait for Event" See the
Bumblebee Kernel Instruction Architecture Handbook for details.
2.15.1.
Clock control into sleep state
The Bumblebee kernel can go to sleep by executing the WFI instruction. See the
Bumblebee Kernel Instruction Architecture Manual for details on how to go to sleep.
The output signal core_sleep_value of the Bumblebee core can be used to indicate
different sleep modes (0 or 1). Sleep mode 0 can usually be used for shallow sleep and
sleep mode 1 is used for deep sleep.Note: After entering Deep Sleep mode, the processor
core will no longer be able to be debugged by the JTAG debug interface.
The key points of the clock control (reference scheme) when the processor core enters
the sleep state are as follows:
Figure 2-1 When the WFI is successfully executed, the output signal
core_wfi_mode of the Bumblebee core is pulled high, indicating that the processor
core is in a sleep state after executing the WFI instruction; the SoC system
level can be used.
Core_wfi_mode Controls the external total gated clock to turn off the processor
core's main operating clock, core_clk.
If the Bumblebee kernel enters deep sleep mode (core_sleep_value is 1), the SoC system can
decide whether to turn off the core's normally open clock core_clk_aon depending on its
actual situation.