User Manual
Page 14
The key points of clock control when the processor core exits the sleep state are as
follows:
If the wakeup is waiting for an interrupt, the interrupt of the Bumblebee
core needs to be processed and distributed by the ECLIC unit. The interrupt
can only wake up the kernel after passing the conditions such as the enable
and priority thresholds.In addition, pay special attention to whether the
processor core's normally open clock (core_clk_aon) is off:
Such as the first 2.1 As described in the section, since TIMER is driven by
core_clk_aon,
Assuming the SoC system level has turned off the processor core's normally open clock
(core_clk_aon), then
The timer unit cannot generate timer interrupts and
software interrupts because it has no clock.
Such as the first 2.1 As described in the section, since ECLIC is driven by
core_clk_aon,:
Assume that the SoC system level has turned off the processor core's normally-on
clock (core_clk_aon), and the external interrupt signal line must be held high until
the SoC system level turns the processor core's normally-on clock (core_clk_aon)
back on.Otherwise, the ECLIC unit of the processor core cannot sample the external
interrupt signal because there is no clock, and the processor core cannot be woken
up.
If it is a wake-up event (Event) or NMI wake-up, the kernel once (by the
core_clk_aon clock) samples the input signal rx_evt (Event signal, active high)
or nmi (NMI signal, rising edge active), from the sleep state Was awakened.In
addition, pay special attention to whether the processor core's normally open
clock (core_clk_aon) is off:
Assume that the SoC system level has turned off the processor core's normally open clock
(core_clk_aon), the input signal
Rx_evt or nmi must be held high after it is pulled high until the SoC
system level turns the processor core's normally open clock (core_clk_aon)
back on.Otherwise, the processor core's Event and NMI sampling logic
cannot be sampled to Event and NMI because there is no clock and cannot
be woken up.