User Manual

Page 14
1. Bumblebee kernel overview
The Bumblebee Processor Core, or Bumblebee core, is a commercial custom made by
Nuclei System Technology in conjunction with Gigadevice for its general purpose MCU
products for IoT or other ultra-low power scenarios. RISC-V processor core.
Note: The Bumblebee core used for this MCU is jointly developed by Nuclei System Technology
and Taiwanese Andes Technology, and Nuclei System Technology provides authorization and
technical support services.At present, Nuclei System Technology can license the mass-proven N200
series of ultra-low-power commercial processor cores, as well as research a variety of high-
performance embedded processor series, and provide customers with customized services.
1.1. Bumblebee kernel feature list
The list of features of the Bumblebee kernel is as follows:
 CPU core (CPU Core)
 The 2-stage variable-length pipeline architecture uses state-of-the-art
processor architecture to achieve the industry's highest energy
efficiency and lowest cost.
 Simple dynamic branch predictor.
 The instruction prefetch unit can prefetch two instructions in order to hide
the instruction fetch delay.
 Supports Machine Mode and User Mode.
 Support for Instruction Set Architecture (ISA, Instruction Set Architecture)
 The Bumblebee kernel supports the 32-bit RISC-V instruction set architecture
and supports a combination of RV32IMAC instruction subsets.
 Hardware supports misaligned memory access operations (Load/Store
instructions)
 Bus interface
 Supports a 32-bit wide standard AHB-Lite system bus interface for accessing external commands
and data.