User Manual

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 Supports 32-bit wide Private Peripheral Interface (PPI) and supports standard APB
Interface protocol for connecting private peripherals.
 Debugging function
 Support for standard jtag interfaces.
 Support for the risc-v debugging standard.
 Support for 4 hardware breakpoints (Hardware Breakpoints).
 Support for sophisticated interactive debugging tools.
 Low power management
 Supports WFI (Wait For Interrupt) and WFE (Wait For Event) to enter sleep mode.
 Two-level sleep mode is supported: shallow sleep and deep sleep.
 Kernel-owned timer unit (Machine Timer, TIMER for short)
 A 64-bit wide real-time timer that supports the generation of timer
interrupts defined by the risc-v standard.
 Enhanced Core Level Interrupt Controller (ECLIC)
 Supports software interrupts, timer interrupts, and external interrupts defined by the risc-v
standard.
 Support dozens of external interrupt sources. For the number and allocation of
interrupt sources, please refer to the data sheet of the specific mcu chip.
 Supports 16 interrupt levels and priorities, and supports software dynamic programmable
modification of interrupt levels and interrupt priority values.
 Interrupt nesting based on interrupt levels is supported.
 Support for fast vector interrupt handling mechanisms.
 Support for fast interrupt biting mechanism.
 Support NMI (Non-Maskable Interrupt).
 Software development tools:
 The Bumblebee kernel supports the RISC-V standard build toolchain and the
Linux/Windows Graphical Integrated Development Environment (IDE).