User Manual

MGC3030/3130
DS40001667E-page 18 Advance Information  2012-2017 Microchip Technology Inc.
4.1 Reset Block
The Reset block combines all Reset sources. It
controls the device system’s Reset signal (SYSRST).
The following is a list of device Reset sources:
•MCLR
: Master Clear Reset pin
• SWR: Software Reset available through GestIC
Library Loader
• WDTR: Watchdog Timer Reset
A simplified block diagram of the Reset block is
illustrated in Figure 4-2.
FIGURE 4-2: SYSTEM RESET BLOCK
DIAGRAM
4.2 Power Control and Clocks
4.2.1 POWER MANAGEMENT UNIT (PMU)
The device requires a 3.3V ±5% supply voltage at VDD.
According to Figure 4-3, the used power domains are
as follows:
• V
DD Domain: This domain is powered by
V
DD = 3.3V ±5% (typical VDD = 3.3V). VDD is the
external power supply for EIO, wake-up logic,
WDTR and internal regulators.
• V
DDC Domain: This domain is powered by
V
DDC = 1.8V. It is generated by an embedded low-
impedance and fast linear voltage regulator. The
voltage regulator is working under all conditions
(also during Deep Sleep mode) preserving the
MGC3X30 data context. V
DDC is the internal
power supply voltage for digital blocks, Reset
block and RC oscillators. An external block
capacitor, C
EFCD, is required on VCAPD pin.
• V
DDA Domain: This domain is powered by
V
DDA = 3.0V. It is generated by an embedded low-
impedance and fast linear voltage regulator.
During Deep Sleep mode, the analog voltage
regulator is switched off. V
DDA is the internal
analog power supply voltage for the ADCs and
the signal conditioning. An external block
capacitor, C
EFCA, is required on VCAPA pin.
• V
DDM Domain: This domain is powered by
V
DDM = 3.3V. VDDM is the internal power supply
voltage for the internal Flash memory. V
DDM is
directly powered through V
DD=3.3V.
FIGURE 4-3: POWER SCHEME BLOCK
DIAGRAM
MCLR
Glitch Filter
Deep sleep
WDTR
Software Reset (SWR)
WDT Time-out
SYSRST
SPU
Digital
Peripherals
Reset Block
Internal Osc.
VDDC Domain
Analog voltage
regulator
Digital voltage
regulator
FLASH
Memory
Wakeup logic
WDTR
EIO
VDDM Domain
V
SS2
V
DD
V
SS1
V
CAPA
V
SS3
ADC
Signal Conditioning Blocks
VDDA Domain
V
CAPD
VDD Domain
V
CAPS