User Manual

 2012-2017 Microchip Technology Inc. Advance Information DS40001667E-page 19
MGC3030/3130
4.2.2 POWER SUPERVISORS
During the Power-up sequence, the system is kept
under Reset condition for approximately 200 µs (Reset
delay: t
RSTDLY
) after the VDD =1.5V voltage is reached
(1.2V minimum). During this delay, the system Reset
will remain low and the VDD should reach typically 2V.
When the Reset delay is elapsed, the system Reset is
released (high) and the system starts the Power-up/
Time-out (t
PWRT
) sequence. The system start depends
on the used V
DD voltage. The Power-up/Time-out
period (t
PWRT
) after Reset takes 36 LSO cycles. (see
Table 4-3).
The system starts when (see Figure 4-4):
• Power-up/Time-out period (t
PWRT
) is elapsed
•V
DD = 3.3V is already reached before the end of
t
PWRT
timing
The power-up sequence begins by increasing the
voltage on the VDD pin (from 0V). If the slope of the VDD
rise time is faster than 4.5 V/ms, the system starts
correctly.
If the slope is less than 4.5 V/ms, the MCLR
pin must
be held low, by external circuitry, until a valid operating
VDD level is reached.
FIGURE 4-4: POWER SUPERVISORS
MCLR
1.5V
V
DD
time
3.3V
t1: t
RSTDLY
: Reset delay typically 200 μs, 120 μs minimum
t2: t
PWRT
: Power-up Time-out
2V
t1
t2