User Manual

2012-2017 Microchip Technology Inc. Advance Information DS40001667E-page 33
MGC3030/3130
FIGURE 5-4: I
2
C™ MASTER READ BIT TIMING DIAGRAM
FIGURE 5-5: I
2
C™ MASTER WRITE BIT TIMING DIAGRAM
312 456789 312 456789 312 456789
A7 A6 A5 A4 A3 A2 A1
1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Address R/W ACK ACK ACKData Data
Address Bits Latched in Data Bits Valid Out Data Bits Valid Out
SCL may be stretched SCL may be stretched
S
P
Start Bit
Stop Bit
SDA
SCL
312 456789 312 456789 312 456789
A7 A6 A5 A4 A3 A2 A1
0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Address R/W ACK ACK ACKData Data
Address Bits Latched in Data Bits Valid Out Data Bits Valid Out
SCL may be stretched SCL may be stretched
S
P
Start Bit
Stop Bit
SDA
SCL