Datasheet

Rev. 1.10 20 May 16, 2011 Rev. 1.10 21 May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Key Data Memory – RAM Structure
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The RAM is a static 16 x 3 -bits RAM which stores key data which keys have been detected
as key data by the key scanning circuit. Each bit in the register corresponds to one key switch.
The bit is set to 1 if the switch has been correctly key data since the last key data register read
operation.
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Reading the key data RAM clears the key data RAM after the key data has been read, so
that future key presses can be identified. If the key data RAM is not read, the key scan data
accumulates. There is no FIFO register in the HT16K33. Key-press order, or whether a key has
been pressed more than once, cannot be determined unless the all key data RAM is read after each
interrupt and before completion of the next keyscan cycle.
●
After the all key data RAM has been read, the INT pin output is cleared along with the INT ag
status. If a key is pressed and held down, the key is reported as key data (and an INT is issued)
only once. The key must be detected as released by the keyscanning circuit before it is key data
again.
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The key data RAM is read only. A write to address 0x40~0x45 is ignored.
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It is strongly recommended that the key data RAM is read only and should be started form address
0X40H only, the key data RAM of address 0X40H ~0X45H should be read continuously and in
one operation.
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There is a one-to-one correspondence between the key data RAM addresses and the Key data
outputs and between the individual bits of a key data RAM word and the key data outputs. The
following shows the mapping from the RAM to the key data output:
ROW3~15 K1 K8 K9 K16
COM1/KS0 40H 41H
COM2/KS1 42H 43H
COM3/KS2 44H 45H
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I
2
C bus display data transfer format
Data byte of I
2
C D7 D6 D5 D4 D3 D2 D1 D0
KS0
K8 K7
K6 K5 K4 K3 K2 K1
0 0 0 K13
K12 K11 K10 K9
KS1
K8 K7
K6 K5 K4 K3 K2 K1
0 0 0 K13
K12 K11 K10 K9
KS2
K8 K7 K6 K5 K4 K3 K2 K1
0 0 0 K13
K12 K11 K10 K9