Datasheet

Beijing Winner Microelectronics Co., Ltd.
9
6.9 FLASH Controller
⚫ Provide bus access in Flash interface;
⚫ Provide arbitration between system bus and data bus;
⚫ Implementation of CACHE;
⚫ Support compatible with different QFlash;
6.10 RSA Encryption
RSA, arithmetic hardware coprocessor, provides Montgomery (FIOS) modular multiplication. The module
implements of RSA algorithm with RSA software library, and supports from 128-bit to 2048-bit.
6.11 Encrypted Hardware Accelerator
The specified length data in the source address will be automatically en-/decrypted, and the result data will
be write to the designated destination address space.
The module support PRNG (Pseudo random Number Generator), SHA1, MD5, RC4, DES, 3DES, AES, CRC.
6.12 I
2
C Controller
I²C Controller connects though APB Interface. Its supports master mode and configurable operating
frequency（100K-400K）.
6.13 Master/Slave SPI Controller
Its support Master/Slave operating mode. The operating frequency is the frequency of system Bus. The
main features of the bus are：
⚫ Provides separate 8-level depth transmit and receive FIFO buffers;
⚫ support Motorola SPI protocol,（CPOL,CPHA）, TI protocol, macrowire protocol in master mode;
⚫ support Motorola SPI protocol（CPOL,CPHA）in slave mode;
⚫ Support full duplex and half duplex;
⚫ support data length up to 65535bit in master mode;
⚫ support data transfer of any bit length in slave mode;
⚫ 1/6 system clock frequency is max frequency of spi_clk in slave mode;