K��� Datasheet KENDRYTE Canaan Inc. ©2019 KENDRYTE.
i About This Guide This document provides the specifications of Kendryte family of chips. Revision History Date Ver. Revision History 2018-09-01 V0.1.0 Initial release 2018-09-13 V0.1.1 Fixing the wrong description in SPI and GPIO 2018-09-14 V0.1.2 Correction of errors in Chapter 1 2018-09-17 V0.1.3 Correction of pin description error in Chapter 2 2018-09-18 V0.1.4 Adding Kendryte system architecture diagram 2018-09-19 V0.1.
About This Guide Copyright Notice Copyright © 2018 Canaan Inc. All rights reserved.
iii Contents About This Guide i Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Copyright Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Chapter1 Overview 1 1.1 AI solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Specifications 5 2.1 Pin Layout . . . . . . . . . . .
Contents iv 3.10 FFT Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 SHA256 Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 Universal Asynchronous Transceiver (UART) . . . . . . . . . . . . . 20 3.13 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 General Purpose Input/Output Interface (GPIO) . . . . . . . . . . . 22 3.15 Direct Memory Access Controller (DMAC) . . . . . . . . . . . . . . . 22 3.
1 Chapter 1 Overview The Kendryte K210 is a system-on-chip (SoC) that integrates machine vision and machine hearing. Using TSMC’s ultra-low-power 28-nm advanced process with dualcore 64-bit processors for better power efficiency, stability and reliability. The SoC strives for ”zero threshold” development and to be deployable in the user’s products in the shortest possible time, giving the product artificial intelligence.
Chapter1 Overview 1.1 1.1.1 AI solution Machine Vision With machine vision capabilities, the Kendryte K210 is a zero-threshold embedded machine vision solution. It can perform convolutional neural network calculations with low power consumption. Capabilities: • Object Detection • Image Classification • Face Detection and Recognition • Obtaining size and coordinates of target in real time • Obtaining type of detected target in real time 1.1.
Chapter1 Overview 3 time, the direction of speech can be determined according to the microphone array, and the camera is rotated to point to the person. 1.2 Architecture Overview DMA GPIO CPU DVP JTAG AES UART RISC-V 64bit RISC-V 64bit SPI FPU RTC FPU OTP I²S KPU FPIOA I²C CNN Accelerator Timer PWM APU SRAM FFT Audio Accelerator WDT SHA256 Kendryte K210 The K210 includes two 64-bit RISC-V CPU cores, each with a built-in independent FPU.
Chapter1 Overview The K210 embeds AES and SHA256 algorithm accelerators to provide users with basic security features. The K210 features high-performance, low-power SRAM and powerful DMA for superior data throughput. K210 has a wide range of peripheral units: DVP, JTAG, OTP, FPIOA, GPIO, UART, SPI, RTC, I2S, I2C, WDT, Timer and PWM, for a large number of application scenarios.
5 Chapter 2 Pin Specifications The K210 uses a well-designed pin layout to ensure that the signals are on the BGA outer ring to allow PCB designers to fanout and route easily, improve electrical performance and reduce design difficulty. Since the K210 contains multiple IO signals from the power domain and different power domains may have different voltages, the following will list the power domains used: Power Group Power Domain Voltage（V） Connected to Name A 0 3.3/1.
Chapter2 Pin Specifications 2.
Chapter2 Pin Specifications 7 Ball Name Type Function A1 IO_37 I/O Multifunctional IO (FPIOA)（Bank 6，Group C） GPIOHS21 A2 IO_36 I/O Multifunctional IO (FPIOA)（Bank 6，Group C） GPIOHS20 A3 IO_35 I/O Multifunctional IO (FPIOA)（Bank 5，Group B） GPIOHS19 A4 IO_33 I/O Multifunctional IO (FPIOA)（Bank 5，Group B） GPIOHS17 A5 IO_31 I/O Multifunctional IO (FPIOA)（Bank 5，Group B） GPIOHS15 A6 IO_29 I/O Multifunctional IO (FPIOA)（Bank 4，Group B） GPIOHS13 A7 IO_27 I/O Multifunctional
Chapter2 Pin Specifications 8 Ball Name Type Function Reset State C12 IO_15 I/O Multifunctional IO (FPIOA)（Bank 2，Group A） GPIO7 D1 IO_43 I/O Multifunctional IO (FPIOA)（Bank 7，Group C） GPIOHS27 D2 IO_42 I/O Multifunctional IO (FPIOA)（Bank 7，Group C） GPIOHS26 D3 VDDIO6C S 3.3V/1.8V supply for FPIOA IO（Bank 6，Group C） VDDIO33 D4 VDD S 0.9V digital core supply VDD D5 VSS S Ground VSS D6 VDD S 0.
Chapter2 Pin Specifications 9 Ball Name Type Function Reset State F11 IO_8 I/O Multifunctional IO (FPIOA)（Bank 1，Group A） GPIO0 F12 IO_9 I/O Multifunctional IO (FPIOA)（Bank 1，Group A） GPIO1 G1 F_D1 I/O Dedicated SPI GPIO (1.8V only) F_D1 G2 F_CS O Dedicated SPI GPIO (1.8V only) F_CS G3 VSS S Ground VSS G4 VSS S Ground VSS G5 VSS S Ground VSS G6 VSS S Ground VSS G7 VDD S 0.9V digital core supply VDD G8 VSS S Ground VSS G9 VDD S 0.
Chapter2 Pin Specifications Function 10 Ball Name Type J10 VSS S J11 IO_2 I/O Multifunctional IO (FPIOA)（Bank 0，Group A） JTAG_TMS J12 IO_3 I/O Multifunctional IO (FPIOA)（Bank 0，Group A） JTAG_TDO K1 F_CLK O Dedicated SPI GPIO (1.8V only) K2 VSS S Ground VSS K3 VSS S Ground VSS K4 VSSPLL S PLL analog ground, noise sensitive K5 VSS S Ground K6 VDDIO18 S 1.8V supply for low voltage IO K7 VSS S Ground K8 VDDIO18 S 1.
Chapter2 Pin Specifications 11 Ball Name Type Function Reset State M9 DVP_D3 I Dedicated DVP D3 input (FLOAT*) M10 DVP_D2 I Dedicated DVP D2 input (FLOAT*) M11 DVP_D1 I Dedicated DVP D1 input (FLOAT*) M12 DVP_D0 I Dedicated DVP D0 input (FLOAT*) Key: Code (FLOAT*) 2.3 *1 Meaning no default function I input O output I/O input/output S power supply Power Supplies Supply Name Voltage（V） Max Current（mA） I/O 3.3V/1.8V VDDIO0A 3.3/1.8V*1 200 I/O 3.3V/1.8V VDDIO1A 3.
Chapter2 Pin Specifications 2.4 12 Supply Name Voltage（V） Max Current（mA） PLL VSSPLL 0 - Reset Circuitry It is recommended to use a 1.8V output MCU power supply monitor IC in order to ensure a stable reset under power-on, power-down and under-voltage conditions. 2.5 Special Pins IO_16 is used for boot mode selection. During power-on reset, pull high to boot from FLASH and pull low to enter ISP mode. After reset, IO_0, IO_1, IO_2, and IO_3 are JTAG pins. IO_4 and IO_5 are ISP pins.
13 Chapter 3 Functional Description 3.
Chapter3 Functional Description Feature D-Cache Details 32KiB×2 Cores 0 and 1 each have a 32 KiB data cache to improve dual-core data read performance On-Chip 8MiB SRAM 8MiB of on-chip SRAM in total, see SRAM chapter for details 3.1.
Chapter3 Functional Description 15 both cores • Support for software interrupts, and each core can trigger cross-core interrupts • Built-in CPU timer interrupt, both cores are freely configurable • Advanced external interrupt management, supporting 64 external interrupt sources, each interrupt source can be configured with 7 priority levels 3.1.
Chapter3 Functional Description 16 Maximum pre-quantisation Maximum fixed point Mode model size (MiB) Non-realtime（＜ 10fps）*1 Flash Capacity*2 floating point model size （MiB） Flash Capacity The internal structure of the KPU is shown below. Main control unit Parameter parsing unit Gs Interface Main memory AXI Bus KPU Arithmetic unitWrite back unit Gm Interface 3.
Chapter3 Functional Description 3.4 17 Static Random-Access Memory (SRAM) The SRAM is split into two parts, 6MiB of on-chip general-purpose SRAM memory and 2MiB of on-chip AI SRAM memory, for a total of 8MiB. The AI SRAM memory is memory allocated for the KPU. They are distributed in a contiguous address space, available both through the normal cached interface of the CPU, but also directly through the non-cached interface.
Chapter3 Functional Description 18 AI SRAM address map： 3.5 Region Access Start Address End Address Size AI SRAM CPU cached 0x80600000 0x807FFFFF 0x200000 AI SRAM CPU non-cached 0x40600000 0x407FFFFF 0x200000 System Controller (SYSCTL) Controls chip clocking and reset and contains the following general system control registers: • PLL frequency • Clock selection • Peripheral clock division ratios • Clock enables • Module resets • DMA handshake signal selection 3.
Chapter3 Functional Description • Dead bit repair support • 64 REGISTER_ENABLE flag bits, can be used as a switch to control the behaviour of some SoC hardware circuits • Can store 128-bit AES encryption and decryption KEY, hardware write-only trusted storage area 3.8 AES Accelerator The AES accelerator is a module for encryption and decryption.
Chapter3 Functional Description • 32-bit or 64-bit input data width • Supports pure-real, pure-imaginary or complex input data • DMA transfer support 3.11 SHA256 Accelerator The SHA256 accelerator is a computational unit used to calculate SHA-256: • SHA-256 calculation • DMA transfer support for input data 3.12 Universal Asynchronous Transceiver (UART) 3.12.
Chapter3 Functional Description RS232 mode • Programmable THRE interrupt – Use THRE interrupt mode to improve serial port performance. After the THRE mode and FIFO mode are selected, the THRE interrupt is triggered if there is less than the threshold in the FIFO. 3.13 Watchdog Timer (WDT) The WDT is a slave peripheral to the APB and is part of the ”common hardware component design.” It has two WDTs: WDT0, WDT1.
Chapter3 Functional Description 3.14 3.14.1 General Purpose Input/Output Interface (GPIO) High speed GPIO There are a total of 32 high-speed GPIO (GPIOHS). They have the following characteristics: • Configurable as input or output • Each IO is an independent interrupt source • Edge-triggered or level-triggered interrupt support • Each IO can be assigned to one of the 48 pins on the FPIOA • Configurable pull-up and pull-down resistors, or high impedance mode 3.14.
Chapter3 Functional Description • Channel lock support, support for internal channel arbitration, sets the privilege values of the main interface bus based on the priority of data transfer • DMAC status output, idle/busy indication • Each DMA transfer has interrupted, transmission completed, etc. status 3.16 Inter-Integrated Circuit Bus (I²C) There are three I²C bus interfaces, each configurable as master or slave by the user.
Chapter3 Functional Description ing other features: • 8-bit, 16-bit or 32-bit configurable bus width • Up to 4 stereo channels per interface • Supports full-duplex communication, independent transmitter and receiver • APB bus clock and I²S SCLK are asynchronous • 12-bit, 16-bit, 20-bit, 24-bit or 32-bit audio data resolution • I²S0 has a 64-byte deep transmit FIFO and 8-byte deep receive FIFO.
Chapter3 Functional Description 3.21 Real Time Clock (RTC) The RTC is a module for keeping track of real time, with the following characteristics: • Support for external high frequency crystal reference • Configurable external crystal frequency and frequency division ratio • Configurable perpetual calendar, configurable items including century, year, month, day, hour, minute, second and week • Can count in seconds and query current time • Supports setting a set of alarms.
26 Chapter 4 Electrical Characteristics Parameter Name Min Typ Max Unit 3.3V/1.8V IO supply voltage V DD - 3.3/1.8 - V 1.8V Digital supply voltage DV DD1.8V - 1.8 - V 1.8V Analog supply voltage AV DD1.8V - 1.8 - V 0.9V Core supply voltage V DD0.9V - 0.9 - V 3.3V IO supply current I3.3V 1 - - mA 1.8V Digital supply current I1.8V 1 - - mA 1.8V Analog supply current I1.8V 2 - - mA 0.9V Core supply current I0.9V 30 - - mA 3.3V/1.
Chapter4 Electrical Characteristics 27 DS[3:0] Min(mA) Typ(mA) Max(mA) 0000 3.2 5.4 8.3 0001 4.7 8.0 12.3 0010 6.3 10.7 16.4 0011 7.8 13.2 20.2 0100 9.4 15.9 24.2 0101 10.9 18.4 28.1 0110 12.4 20.9 31.8 0111 13.9 23.4 35.5 DS[3:0] Min(mA) Typ(mA) Max(mA) 0000 5.0 7.6 11.2 0001 7.5 11.4 16.8 0010 10.0 15.2 22.3 0011 12.4 18.9 27.8 0100 14.9 22.6 33.3 0101 17.4 26.3 38.7 0110 19.8 30.0 44.1 0111 22.3 33.7 49.
28 Chapter 5 Package information The chip is packaged in BGA144 with 12 balls on each side. The chip size is 8x8x0.953mm (BGA144C65P12X12_800X800X95). The package uses flip chip technology to give the chip the best electrical characteristics, and good heat dissipation.
Chapter5 Package information 29
