Datasheet
Table Of Contents
- About This Guide
- Chapter1 Overview
- Chapter2 Pin Specifications
- Chapter3 Functional Description
- 3.1 CPU
- 3.2 Neural Network Processor (KPU)
- 3.3 Audio Processor (APU)
- 3.4 Static Random-Access Memory (SRAM)
- 3.5 System Controller (SYSCTL)
- 3.6 Field Programmable IO Array (FPIOA/IOMUX)
- 3.7 One-Time Programmable Memory (OTP)
- 3.8 AES Accelerator
- 3.9 Digital Video Port (DVP)
- 3.10 FFT Accelerator
- 3.11 SHA256 Accelerator
- 3.12 Universal Asynchronous Transceiver (UART)
- 3.13 Watchdog Timer (WDT)
- 3.14 General Purpose Input/Output Interface (GPIO)
- 3.15 Direct Memory Access Controller (DMAC)
- 3.16 Inter-Integrated Circuit Bus (I²C)
- 3.17 Serial Peripheral Interface (SPI)
- 3.18 Inter-Integrated Sound (I²S)
- 3.19 TIMER
- 3.20 Read Only Memory (ROM)
- 3.21 Real Time Clock (RTC)
- 3.22 Pulse Width Modulation (PWM)
- Chapter4 Electrical Characteristics
- Chapter5 Package information
5
Chapter 2
Pin Specifications
The K210 uses a well-designed pin layout to ensure that the signals are on the
BGA outer ring to allow PCB designers to fanout and route easily, improve electri-
cal performance and reduce design difficulty.
Since the K210 contains multiple IO signals from the power domain and differ-
ent power domains may have different voltages, the following will list the power
domains used:
Power Group Power Domain Voltage（V） Connected to Name
A 0 3.3/1.8 Other domains in group VDDIO0A
A 1 3.3/1.8 Other domains in group VDDIO1A
A 2 3.3/1.8 Other domains in group VDDIO2A
B 3 3.3/1.8 Other domains in group VDDIO3B
B 4 3.3/1.8 Other domains in group VDDIO4B
B 5 3.3/1.8 Other domains in group VDDIO5B
C 6 3.3/1.8 Other domains in group VDDIO6C
C 7 3.3/1.8 Other domains in group VDDIO7C
LV IO LV IO 1.8 Independent VDDIO18
OTP OTP 1.8 Independent VDDOTP
PLL PLL 0.9 Independent VDDPLL
Core Core 0.9 Independent VDD