Datasheet
Table Of Contents
- About This Guide
- Chapter1 Overview
- Chapter2 Pin Specifications
- Chapter3 Functional Description
- 3.1 CPU
- 3.2 Neural Network Processor (KPU)
- 3.3 Audio Processor (APU)
- 3.4 Static Random-Access Memory (SRAM)
- 3.5 System Controller (SYSCTL)
- 3.6 Field Programmable IO Array (FPIOA/IOMUX)
- 3.7 One-Time Programmable Memory (OTP)
- 3.8 AES Accelerator
- 3.9 Digital Video Port (DVP)
- 3.10 FFT Accelerator
- 3.11 SHA256 Accelerator
- 3.12 Universal Asynchronous Transceiver (UART)
- 3.13 Watchdog Timer (WDT)
- 3.14 General Purpose Input/Output Interface (GPIO)
- 3.15 Direct Memory Access Controller (DMAC)
- 3.16 Inter-Integrated Circuit Bus (I²C)
- 3.17 Serial Peripheral Interface (SPI)
- 3.18 Inter-Integrated Sound (I²S)
- 3.19 TIMER
- 3.20 Read Only Memory (ROM)
- 3.21 Real Time Clock (RTC)
- 3.22 Pulse Width Modulation (PWM)
- Chapter4 Electrical Characteristics
- Chapter5 Package information
13
Chapter 3
Functional Description
3.1 CPU
The chip contains a high-performance, low power RISC-V ISA-based dual core 64-bit
CPU with the following features:
Feature Details
Core Count 2
cores
Dual-core processor, each core with independent FPU
Bit Width 64 bit 64-bit CPU bit width for high-performance algorithm
calculations with sufficient computational bandwidth
Frequency 400MHz Frequency adjustable, can be changed by adjusting PLL VCO
and frequency dividers
ISA
extensions
IMAFDC Based on RISC-V 64-bit IMAFDC (RV64GC), suitable for
general tasks
FPU Double
Preci-
sion
With multiply, divide and square root operations; supports
single-precision and double-precision floating-point
calculations
Platform
Interrupts
PLIC Supports advanced interrupt management; with 64 external
interrupt sources routeable to 2 cores
Local
Interrupts
CLINT With built-in CPU timer interrupt and cross-core interrupt
I-Cache 32KiB×2 Cores 0 and 1 each have a 32 KiB instruction cache to
improve dual-core instruction read performance