Datasheet

13
Chapter 3
Functional Description
3.1 CPU
The chip contains a high-performance, low power RISC-V ISA-based dual core 64-bit
CPU with the following features:
Feature Details
Core Count 2
cores
Dual-core processor, each core with independent FPU
Bit Width 64 bit 64-bit CPU bit width for high-performance algorithm
calculations with sufficient computational bandwidth
Frequency 400MHz Frequency adjustable, can be changed by adjusting PLL VCO
and frequency dividers
ISA
extensions
IMAFDC Based on RISC-V 64-bit IMAFDC (RV64GC), suitable for
general tasks
FPU Double
Preci-
sion
With multiply, divide and square root operations; supports
single-precision and double-precision floating-point
calculations
Platform
Interrupts
PLIC Supports advanced interrupt management; with 64 external
interrupt sources routeable to 2 cores
Local
Interrupts
CLINT With built-in CPU timer interrupt and cross-core interrupt
I-Cache 32KiB×2 Cores 0 and 1 each have a 32 KiB instruction cache to
improve dual-core instruction read performance