Datasheet

Chapter3 Functional Description 14
Feature Details
D-Cache 32KiB×2 Cores 0 and 1 each have a 32 KiB data cache to improve
dual-core data read performance
On-Chip
SRAM
8MiB 8MiB of on-chip SRAM in total, see SRAM chapter for
details
3.1.1 CPU ISA Features
• Powerful dual-core 64-bit open architecture-based processor with rich commu-
nity resources
• I extension: Base Integer Instruction Set
• M extension: integer multiplication and division; hardware acceleration to
achieve high performance integer multiplication and division
• A extension: atomic operations, hardware implementation of the atomic opera-
tions required by operating systems
• C extension: compressed instructions, which can achieve higher code density
and operation efficiency
• Support for different privilege levels to improve safety
3.1.2 FPU Specifications
• IEEE754-2008 compliant high-performance pipelined FPU
• Core 0 and Core 1 each have a separate FPU, and both cores are capable of high
performance hardware floating point calculations
• F extension: single-precision floating point instructions
• D extension: double-precision floating point instructions
• Hardware single-precision and double-precision division
• Hardware single-precision and double-precision square roots
3.1.3 Advanced Interrupt Management Capability
The PLIC controller of the RISC-V CPU supports flexible advanced interrupt man-
agement. It can be configured with 64 external interrupt sources in 7 priority
levels. Both cores can be configured independently:
• Interrupt management and interrupt routing can be controlled independently for