Datasheet

Chapter3 Functional Description 17
3.4 Static Random-Access Memory (SRAM)
The SRAM is split into two parts, 6MiB of on-chip general-purpose SRAM memory and
2MiB of on-chip AI SRAM memory, for a total of 8MiB. The AI SRAM memory is memory
allocated for the KPU. They are distributed in a contiguous address space, avail-
able both through the normal cached interface of the CPU, but also directly through
the non-cached interface.
SRAM address map：
Region Access Start Address End Address Size
General-purpose SRAM CPU cached 0x80000000 0x805FFFFF 0x600000
AI SRAM CPU cached 0x80600000 0x807FFFFF 0x200000
General-purpose SRAM CPU non-cached 0x40000000 0x405FFFFF 0x600000
AI SRAM CPU non-cached 0x40600000 0x407FFFFF 0x200000
3.4.1 General Purpose SRAM
The general purpose SRAM memory is accessible at all times during normal opera-
tion of the chip. The memory is divided into two banks, MEM0 and MEM1, and the DMA
controller can operate in both banks at the same time.
** General-purpose SRAM address map：**
Region Access Start Address End Address Size
MEM0 CPU cached 0x80000000 0x803FFFFF 0x400000
MEM1 CPU cached 0x80400000 0x805FFFFF 0x200000
MEM0 CPU non-cached 0x40000000 0x403FFFFF 0x400000
MEM1 CPU non-cached 0x40400000 0x405FFFFF 0x200000
3.4.2 AI SRAM
The AI SRAM memory is only accessible if the following conditions are met:
• PLL1 enabled and clock system configuration is correct
• KPU not performing neural network calculations