Datasheet

Chapter3 Functional Description 18
AI SRAM address map：
Region Access Start Address End Address Size
AI SRAM CPU cached 0x80600000 0x807FFFFF 0x200000
AI SRAM CPU non-cached 0x40600000 0x407FFFFF 0x200000
3.5 System Controller (SYSCTL)
Controls chip clocking and reset and contains the following general system con-
trol registers:
• PLL frequency
• Clock selection
• Peripheral clock division ratios
• Clock enables
• Module resets
• DMA handshake signal selection
3.6 Field Programmable IO Array (FPIOA/IOMUX)
FPIOA allows users to map 255 internal functions to 48 free IOs on the chip:
• Programmable IO function selection
• 8 drive strength options for outputs
• Selectable internal pull-up resistors
• Selectable internal pull-down resistors
• Schmitt trigger option for inputs
• Slew rate control for outputs
• Selectable internal input level
3.7 One-Time Programmable Memory (OTP)
OTP is a one-time programmable memory unit. The specifications are as follows:
• Large 128Kbit storage capacity
• Internally divided into multiple BLOCKs with different capacity; each with a
separate write protection bit