Datasheet

Chapter3 Functional Description 19
• Dead bit repair support
• 64 REGISTER_ENABLE flag bits, can be used as a switch to control the behaviour
of some SoC hardware circuits
• Can store 128-bit AES encryption and decryption KEY, hardware write-only
trusted storage area
3.8 AES Accelerator
The AES accelerator is a module for encryption and decryption. The specifications
are as follows:
• ECB, CBC, and GCM encryption methods
• 128-bit, 192-bit or 256-bit key
• Key can be configured by software and protected by hardware circuit
• DMA transfer support
3.9 Digital Video Port (DVP)
The DVP is a camera interface module with the following features:
• Supports cameras with a DVP interface
• Supports camera configuration using SCCB protocol
• Maximum frame size 640x480
• Supports YUV422 and RGB565 format image input
• Can output images to both KPU and display
– Output format to KPU: RGB888 or the Y component of YUV422 input
– Output format to display: RGB565
• Interrupt can be sent to CPU for start-of-frame or completion of frame image
transmission
3.10 FFT Accelerator
The FFT accelerator is a hardware implementation of the Fast Fourier Transform
(FFT).
• 64-point, 128-point, 256-point or 512-point length
• FFT and IFFT operation modes