Datasheet

Chapter3 Functional Description 20
32-bit or 64-bit input data width
Supports pure-real, pure-imaginary or complex input data
DMA transfer support
3.11 SHA256 Accelerator
The SHA256 accelerator is a computational unit used to calculate SHA-256:
SHA-256 calculation
DMA transfer support for input data
3.12 Universal Asynchronous Transceiver (UART)
3.12.1 High Speed UART
High speed UART UARTHS(UART0)
Baud rate up to 5Mbps
8-byte transmit and receive FIFO
Programmable THRE interrupt
Does not support hardware flow control or other modem control signals, or
synchronous serial data protocols
3.12.2 General Purpose UART
UART1, UART2 and UART3 are general purpose UARTs and support asynchronous com-
munication RS232/RS485/IRDA), baud rate up to 5Mbps, hardware flow control using
CTS/RTS or (XON/XOFF). All three interfaces can be accessed by DMA or directly by
the CPU.
8-byte transmit and receive FIFO
Asynchronous clock support
In order to cope with the CPU’s baud rate requirement for data synchro-
nization, the UART can configure the data clock separately for transmit
and receive. The full-duplex mode can ensure the synchronization of data
in the two clock domains.
RS485 interface support
The UART can be configured by software into RS485 mode. The default is