Datasheet

Chapter3 Functional Description 21
RS232 mode
• Programmable THRE interrupt
– Use THRE interrupt mode to improve serial port performance. After the THRE
mode and FIFO mode are selected, the THRE interrupt is triggered if there
is less than the threshold in the FIFO.
3.13 Watchdog Timer (WDT)
The WDT is a slave peripheral to the APB and is part of the ”common hardware
component design.” It has two WDTs: WDT0, WDT1. The watchdog timer contains the
following modules:
• An APB slave interface
• A register module that synchronizes the current counter
• An interrupt/system reset module and logic control circuit with down counter
• A synchronous clock domain to support asynchronous clock synchronization
The watchdog timer supports the following settings:
• APB bus width can be configured to 8, 16, and 32 bits
• The clock counter is decremented from a certain set value to 0 to indicate
timeout
• Optional external clock enable signal to control the counter’s count rate
• Upon clock timeout the WDT can perform the following tasks:
– Generate a system reset signal
– First generate an interrupt, even if the bit has been cleared by the in-
terrupt service, and subsequently it will generate a system reset signal.
• Configurable duty cycle
• Programmable or hardware set counter start value
• Counter reset protection
• Pause mode, when the external pause signal is enabled
• WDT accidental disable protection
• Test mode for counter function test (decrement operation)
• External asynchronous clock support. When this function is enabled, a clock
interrupt and a system reset signal will be generated even if the APB bus
clock is off.