Datasheet
Table Of Contents
- About This Guide
- Chapter1 Overview
- Chapter2 Pin Specifications
- Chapter3 Functional Description
- 3.1 CPU
- 3.2 Neural Network Processor (KPU)
- 3.3 Audio Processor (APU)
- 3.4 Static Random-Access Memory (SRAM)
- 3.5 System Controller (SYSCTL)
- 3.6 Field Programmable IO Array (FPIOA/IOMUX)
- 3.7 One-Time Programmable Memory (OTP)
- 3.8 AES Accelerator
- 3.9 Digital Video Port (DVP)
- 3.10 FFT Accelerator
- 3.11 SHA256 Accelerator
- 3.12 Universal Asynchronous Transceiver (UART)
- 3.13 Watchdog Timer (WDT)
- 3.14 General Purpose Input/Output Interface (GPIO)
- 3.15 Direct Memory Access Controller (DMAC)
- 3.16 Inter-Integrated Circuit Bus (I²C)
- 3.17 Serial Peripheral Interface (SPI)
- 3.18 Inter-Integrated Sound (I²S)
- 3.19 TIMER
- 3.20 Read Only Memory (ROM)
- 3.21 Real Time Clock (RTC)
- 3.22 Pulse Width Modulation (PWM)
- Chapter4 Electrical Characteristics
- Chapter5 Package information

Chapter3 Functional Description 22
3.14 General Purpose Input/Output Interface (GPIO)
3.14.1 High speed GPIO
There are a total of 32 high-speed GPIO (GPIOHS). They have the following charac-
teristics:
• Configurable as input or output
• Each IO is an independent interrupt source
• Edge-triggered or level-triggered interrupt support
• Each IO can be assigned to one of the 48 pins on the FPIOA
• Configurable pull-up and pull-down resistors, or high impedance mode
3.14.2 General purpose GPIO
There are 8 general-purpose GPIOs with the following characteristics:
• All 8 IOs are one interrupt source
• Configurable as input or output
• Edge-triggered or level-triggered interrupt support
• Each IO can be assigned to one of the 48 pins on the FPIOA
• Configurable pull-up and pull-down resistors, or high impedance mode
3.15 Direct Memory Access Controller (DMAC)
The DMAC is highly configurable, highly programmable, and highly efficient at
transferring data in bus mode. The DMAC controller supports multi-master and multi-
channel. DMAC has the following features:
• Memory-memory, memory-peripheral, peripheral-memory or peripheral-peripheral
transfers
• Independent core and slave clocks
• The main interface can turn off its clock to save power when all peripherals
are inactive
• Up to eight channels, each with their own source and destination pair
• Each channel data can only transmit in one direction at a time
• Input pin can dynamically select the destination size