Datasheet

Chapter3 Functional Description 23
• Channel lock support, support for internal channel arbitration, sets the priv-
ilege values of the main interface bus based on the priority of data transfer
• DMAC status output, idle/busy indication
• Each DMA transfer has interrupted, transmission completed, etc. status
3.16 Inter-Integrated Circuit Bus (I²C)
There are three I²C bus interfaces, each configurable as master or slave by the
user.
• Standard mode (0 to 100Kb/s)
• Fast mode (<= 400Kb/s)
• 7-bit/10-bit addressing mode
• Bulk transfer mode
• Interrupt or polling mode operation
3.17 Serial Peripheral Interface (SPI)
There are four SPI interfaces; of which SPI0, SPI1 and SPI3 only support MASTER
mode, and SPI2 only supports SLAVE mode.
• Support for 1/2/4/8 wire full duplex mode
• SPI0, SPI1, and SPI2 support up to 25MHz clock (TBC)
• SPI3 supports up to 100MHz clock (TBC)
• 32-bit wide, 32-byte deep FIFO
• Independently Masked Interrupts: host conflict, transmit FIFO overflow, trans-
mit FIFO empty, receive FIFO full, receive FIFO underflow, receive FIFO over-
flow
• Support for DMA transfers
• Support for dual-edge DDR transmission mode
• SPI3 supports XIP
3.18 Inter-Integrated Sound (I²S)
There are 3 I²S interfaces on board (I2S0, I2S1 and I2S20, all of which only sup-
port MASTER mode. I2S0 can be connected to the voice processing module to enable
voice enhancement and sound source orientation. All interfaces support the follow-