Datasheet

Chapter3 Functional Description 24
ing other features:
• 8-bit, 16-bit or 32-bit configurable bus width
• Up to 4 stereo channels per interface
• Supports full-duplex communication, independent transmitter and receiver
• APB bus clock and I²S SCLK are asynchronous
• 12-bit, 16-bit, 20-bit, 24-bit or 32-bit audio data resolution
• I²S0 has a 64-byte deep transmit FIFO and 8-byte deep receive FIFO. Other
interfaces have 8-byte deep transmit and receive FIFOs
• Support for DMA transfers
• Programmable FIFO threshold
3.19 TIMER
The system has three TIMER modules with the following characteristics:
• 32-bit counter width
• Configurable as up or down counter
• Independent clocks
• Configurable polarity for each interrupt
• Configurable individual or combined interrupt output flags
• Each timer has a read/write consistent register
• Timer reload output, switches whenever the timer counter is reloaded
• Output PWM mode，0 ％-100% duty cycle
3.20 Read Only Memory (ROM)
The AXI ROM is responsible for copying the user’s application program from SPI
FLASH to the SRAM of the chip.
• Support for AES-128-CBC firmware decryption
• UOP mode to program FLASH
• SHA256 firmware integrity check for tamper resistance
• OTP configurable to disable UOP mode, SHA256 check, and AES decryption
• Support for entering TURBO mode, which enables the chip and its peripherals to
run at higher frequencies during startup