Datasheet
Table Of Contents
- About This Guide
- Chapter1 Overview
- Chapter2 Pin Specifications
- Chapter3 Functional Description
- 3.1 CPU
- 3.2 Neural Network Processor (KPU)
- 3.3 Audio Processor (APU)
- 3.4 Static Random-Access Memory (SRAM)
- 3.5 System Controller (SYSCTL)
- 3.6 Field Programmable IO Array (FPIOA/IOMUX)
- 3.7 One-Time Programmable Memory (OTP)
- 3.8 AES Accelerator
- 3.9 Digital Video Port (DVP)
- 3.10 FFT Accelerator
- 3.11 SHA256 Accelerator
- 3.12 Universal Asynchronous Transceiver (UART)
- 3.13 Watchdog Timer (WDT)
- 3.14 General Purpose Input/Output Interface (GPIO)
- 3.15 Direct Memory Access Controller (DMAC)
- 3.16 Inter-Integrated Circuit Bus (I²C)
- 3.17 Serial Peripheral Interface (SPI)
- 3.18 Inter-Integrated Sound (I²S)
- 3.19 TIMER
- 3.20 Read Only Memory (ROM)
- 3.21 Real Time Clock (RTC)
- 3.22 Pulse Width Modulation (PWM)
- Chapter4 Electrical Characteristics
- Chapter5 Package information
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Contents
About This Guide i
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Copyright Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Chapter1 Overview 1
1.1 AI solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter2 Pin Specifications 5
2.1 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Special Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter3 Functional Description 13
3.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Neural Network Processor (KPU) . . . . . . . . . . . . . . . . . . . 15
3.3 Audio Processor (APU) . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Static Random-Access Memory (SRAM) . . . . . . . . . . . . . . . . . 17
3.5 System Controller (SYSCTL) . . . . . . . . . . . . . . . . . . . . . 18
3.6 Field Programmable IO Array (FPIOA/IOMUX) . . . . . . . . . . . . . 18
3.7 One-Time Programmable Memory (OTP) . . . . . . . . . . . . . . . . . 18
3.8 AES Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9 Digital Video Port (DVP) . . . . . . . . . . . . . . . . . . . . . . 19