User's Manual
Table Of Contents
15
5
S
P
I
_
C
S
0
G
P
I
O
#
10
S
P
I
bus chip select
0
6
REF_CLK0
G
P
I
O
#
38
Reference clock output
7
PERST_N
G
P
I
O
#
36
P
C
I
e
device reset
8
WDT_RST_N
G
P
I
O
#
37
Watchdog reset
9
EPHY_LED4
JTAG_RST_
N
G
P
I
O
#
39
10
EPHY_LED3
JTAG_CLK
G
P
I
O
#
40
11
EPHY_LED2
JTAG_TMS
G
P
I
O
#
41
12
EPHY_LED1
J
TA
G
_
T
D
I
G
P
I
O
#
42
13
EPHY_LED0
JTAG_TDO
G
P
I
O
#
43
14
PORST_N
CPU reset
15
UART_TXD1
PWM_CH0
G
P
I
O
#
45
Port 1 date transmission
16
UART_RXD1
PWM_CH1
G
P
I
O
#
46
Port 1 date reception
17
I
2
S
_
S
D
I
PCMDRX
G
P
I
O
#0
I
2
S
date input
18
I
2
S
_
S
D
O
PCMDTX
G
P
I
O
#1
I
2
S
date output
19
I
2
S
_
W
S
PCMCLK
G
P
I
O
#2
I
2
S
sound channel
selection
,
0
:
left
；
1
:
right
20
I
2
S
_
C
L
K
PCMFS
G
P
I
O
#
3
I
2
S
21
GND
22
ANT
Antennal RF interface(not
connect)
23
GND
24
I
2
C
_
S
C
L
K
G
P
I
O
#
4
I
2
C
25
I
2
C
_
S
D
G
P
I
O
#
5
I
2
C
26
S
P
I
_
C
S
1
G
P
I
O
#
6
SP 1
27
S
P
I
_
C
L
K
G
P
I
O
#
7
S
P
I
28
S
P
I
_
M
I
S
O
G
P
I
O
#
9
S
P
I
29
S
P
I
_
M
O
S
I
G
P
I
O
#
8
S
P
I
30
G
P
I
O
0
G
P
I
O
#
11
31
UART_TXD
0
G
P
I
O
#12
Port 0 date output
32
UART_RXD
0
G
P
I
O
#13
Port 0 date input
33
WLED_N
G
P
I
O
#44
W
i
F
i
L
E
D
34
M
D
I
_
R
P
_
P
0
35
M
D
I
_
R
N
_
P
0