Data Sheet

1026
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
2 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the on-
chip flash size minus half a row. Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
39.1.1.7 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master
SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low
Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the
GCLK_SERCOM_SLOW is not requested. Errata reference: 12003
Fix/Workaround:
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-
out (CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt
(INTFLAG.SSL) can be generated. Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug
mode. Instead, it is stopped when the current byte transaction is completed
and the corresponding interrupt is triggered if enabled. Errata reference:
12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.