Data Sheet

107
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 5:0 – ID[5:0]: Generic Clock Selection ID
These bits select the generic clock that will be configured. The value of the ID bit group versus module instance is
shown in
Table 14-4.
0x4 GCLKGEN4 Generic clock generator 4
0x5 GCLKGEN5 Generic clock generator 5
0x6 GCLKGEN6 Generic clock generator 6
0x7 GCLKGEN7 Generic clock generator 7
0x8 GCLKGEN8 Generic clock generator 8
0x9-0xF Reserved
Table 14-4. Generic Clock Selection ID
Value Name Description
0x00 GCLK_DFLL48M_REF DFLL48M Reference
0x01 GCLK_DPLL FDPLL96M input clock source for reference
0x02 GCLK_DPLL_32K FDPLL96M 32kHz clock for FDPLL96M internal lock timer
0x03 GCLK_WDT WDT
0x04 GCLK_RTC RTC
0x05 GCLK_EIC EIC
0x06 GCLK_USB USB
0x07 GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0
0x08 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1
0x09 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2
0x0A GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3
0x0B GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4
0x0C GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5
0x0D GCLK_EVSYS_CHANNEL_6 EVSYS_CHANNEL_6
0x0E GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7
0x0F GCLK_EVSYS_CHANNEL_8 EVSYS_CHANNEL_8
0x10 GCLK_EVSYS_CHANNEL_9 EVSYS_CHANNEL_9
0x11 GCLK_EVSYS_CHANNEL_10 EVSYS_CHANNEL_10
0x12 GCLK_EVSYS_CHANNEL_11 EVSYS_CHANNEL_11
Table 14-3. Generic Clock Generator (Continued)
GEN[3:0] Name Description