Data Sheet

114
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
14.8.5 Generic Clock Generator Division
This register allows the user to configure one of the generic clock generators, as specified in the GENDIV.ID bit group.
To write to the GENDIV register, do a 32-bit write with all configurations and the ID.
To read the GENDIV register, first do an 8-bit write to the GENDIV.ID bit group with the ID of the generic clock generator
whose configuration is to be read, and then read the GENDIV register.
Name: GENDIV
Offset: 0x8
Reset: 0x00000000
Property: -
z Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 23:8 – DIV[15:0]: Division Factor
These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has
can be seen in Table 14-11. Writes to bits above the specified number will be ignored.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DIV[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DIV[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
ID[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000