Data Sheet

144
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
15.8.11 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x34
Reset: 0x00
Property: Write-Protected
z Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 0 – CKRDY: Clock Ready Interrupt Enable
0: The Clock Ready interrupt is disabled.
1: The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
Bit 76543210
CKRDY
AccessRRRRRRRR/W
Reset00000000