Data Sheet

278
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Figure 19-3. Memory Sections
The size of the descriptor and write-back memory sections is dependant on most significant enabled DMA channel, as
shown below:
For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are
required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can share memory
section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for
a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory
and write-back memory in the same section is that it requires less SRAM. In addition, the latency from fetching the first
descriptor of a transaction to the first burst transfer is executed, is reduced.
Channel 0 – Descriptor n-1
Channel 0 – Last Descriptor
DESCADDR
DESCADDR
Device Memory Space
BASEADDR
Channel 0 – First Descriptor
Channel 1 – First Descriptor
Channel 2 – First Descriptor
Channel n – First Descriptor
Descriptor Section
WRBADDR Channel 0 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Channel 2 Ongoing Descriptor
Channel n Ongoing Descriptor
Write-Back Section
Undefined
Undefined
Undefined
Undefined
Undefined
SRCADDR
DSTADDR
BTCTRL
DESCADDR
BTCNT
SRCADDR
DSTADDR
BTCTRL
DESCADDR
BTCNT
SRCADDR
DSTADDR
BTCTRL
0x00000000
BTCNT
Size 128bits MostSignificantEnabledChannelNumber 1+()⋅=