Data Sheet

313
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.1.12 Busy Channels
Name: BUSYCH
Offset: 0x28
Reset: 0x00000000
Property: -
z Bits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 11:0 – BUSYCHx [x=11..0]: Busy Channel x
This bit is cleared when the channel trigger action for DMA channel x is complete, when a bus error for DMA chan-
nel x is detected, or when DMA channel x is disabled.
This bit is set when DMA channel x starts a DMA transfer.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8
AccessRRRRRRRR
Reset00000000
Bit 76543210
BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0
AccessRRRRRRRR
Reset00000000