Data Sheet

327
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
19.8.1.22 Channel Interrupt Flag Status and Clear
Name: CHINTFLAG
Offset: 0x4E
Reset: 0x00
Property: -
z Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 2 – SUSP: Channel Suspend
This flag is cleared by writing a one to it.
This bit is set when a block transfer with suspend block action is completed, when a software suspend command is
executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Suspend interrupt flag for the corresponding channel.
For details on available software commands, refer to Table 19-6.
For details on available event input actions, refer to Table 19-10.
For details on available block actions, refer to Table 19-14.
z Bit 1 – TCMPL: Transfer Complete
This flag is cleared by writing a one to it.
This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt flag for the corresponding channel.
z Bit 0 – TERR: Transfer Error
This flag is cleared by writing a one to it.
This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Error interrupt flag for the corresponding channel.
Bit 76543210
SUSP TCMPL TERR
AccessRRRRRR/WR/WR/W
Reset00000000