Data Sheet

372
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
21.8.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00
Property: Write-Protected
z Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 1 – ERROR: Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit clears the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
z Bit 0 – READY: NVM Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit clears the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
Bit 76543210
ERROR READY
AccessRRRRRRR/WR/W
Reset00000000