Data Sheet

38
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
10.4.2 Configuration
CM0+ 0
DSU 1
High-Speed Bus SLAVES
Internal Flash
0
AHB-APB Bridge A
1
AHB-APB Bridge B
2
AHB-APB Bridge C
3
MTB
Multi-Slave
MASTERS
USB
DMAC WB DMAC Fetch
CM0+
4
DMAC Data DSU
6
SRAM
DSU 1
MTB
USB
DMAC WB
DMAC Fetch
Priviledged SRAM-access
MASTERS
DSU 2
DMAC Data
4
5
0123
65
SLAVE ID
SRAM PORT ID
MASTER ID
Table 10-4. Bus Matrix Masters
Bus Matrix Masters Master ID
CM0+ - Cortex M0+ Processor 0
DSU - Device Service Unit 1
DMAC - Direct Memory Access Controller / Data Access 2
Table 10-5. Bus Matrix Slaves
Bus Matrix Slaves Slave ID
Internal Flash Memory 0
AHB-APB Bridge A 1
AHB-APB Bridge B 2
AHB-APB Bridge C 3
SRAM Port 4 - CM0+ Access 4
SRAM Port 5 - DMAC Data Access 5
SRAM Port 6 - DSU Access 6