Data Sheet

401
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Writing a one to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR,
WRCONFIG.SLEWLIM, WRCONFIG.ODRAIN, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN
and WRCONFIG.PINMASK values.
This bit will always read as zero.
z Bit 29 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 28 – WRPMUX: Write PMUX
This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or
not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
0: The PMUXn registers of the selected pins will not be updated.
1: The PMUXn registers of the selected pins will be updated.
Writing a zero to this bit has no effect.
Writing a one to this bit updates the pin multiplexer configuration of the selected pins with the written WRCON-
FIG.PMUX value.
This bit will always read as zero.
z Bits 27:24 – PMUX[3:0]: Peripheral Multiplexing
These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by
the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.
These bits will always read as zero.
z Bit 23 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 22 – DRVSTR: Output Driver Strength Selection
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
z Bits 21:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 18 – PULLEN: Pull Enable
This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
z Bit 17 – INEN: Input Enable
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
z Bit 16 – PMUXEN: Peripheral Multiplexer Enable
This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PIN-
MASK and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
z Bits 15:0 – PINMASK[15:0]: Pin Mask for Multiple Pin Configuration
These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.
0: The configuration of the corresponding I/O pin in the half-word group will be left unchanged.