Data Sheet

506
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
26.8.8 Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property:
z Bits 31:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 2– CTRLB: CTRLB Synchronization Busy
Writing CTRLB when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.CTRLB
bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB
error will be generated.
0: CTRLB synchronization is not busy.
1: CTRLB synchronization is busy.
z Bit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNC-
BUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and
an APB error will be generated.
0: Enable synchronization is not busy.
1: Enable synchronization is busy.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
CTRLB ENABLE SWRST
AccessRRRRRRRR
Reset00000000