Data Sheet

525
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
If not acknowledge is sent, the I
2
C slave will wait for a new start condition and address match.
Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I
2
C slave
command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on
STATUS.DIR.
Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Receiving Address Packets (SCLSM=1)
When SCLSM is one, the I
2
C slave only stretches the SCL line after an acknowledge according to Figure 27-11. When
the I
2
C slave is properly configured, it will wait for a start condition to be detected. When a start condition is detected, the
successive address packet will be received and checked by the address match logic. If the received address is not a
match, the packet is rejected and the I
2
C slave waits for a new start condition. If the address matches, the acknowledge
action (CTRLB.ACKACT) is automatically sent and the Address Match bit in the Interrupt Flag register
(INTFLAG.AMATCH) is set. SCL will be stretched until the I
2
C slave clears INTFLAG.AMATCH. Because the I
2
C slave
holds the clock by forcing SCL low, the software is given unlimited time to respond to the address.
The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register
(STATUS.DIR), and the bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to
the I
2
C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to
software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are
intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I
2
C master, a one can be written to INTFLAG.AMATCH to clear it.
Receiving and Transmitting Data Packets (SCLSM=0)
After the I
2
C slave has received an address packet, it will respond according to the direction either by waiting for the data
packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or
sent, INTFLAG.DRDY will be set. Then, if the I
2
C slave was receiving data, it will send an acknowledge according to
CTRLB.ACKACT.
Case 1: Data received
INTFLAG.DRDY is set, and SCL is held low pending SW interaction.
Case 2: Data sent
When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, the
I
2
C slave must expect a stop or a repeated start to be received. The I
2
C slave must release the data line to allow the I
2
C
master to generate a stop or repeated start.
Upon stop detection, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I
2
C slave
will return to the idle state.
High Speed Mode
When the I
2
C slave is configured in High-speed mode (CTRLA.SPEED=0x2) with SCLSM set to one, switching between
Full-speed and High-speed modes is automatic. When the slave recognizes a START followed by a master code
transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit
(STATUS.HS). The slave will then remain in High-speed mode until a STOP is received.
10-Bit Addressing
When 10-bit addressing is enabled (ADDR.TENBITEN=1) the two address bytes following a START will be checked
against the 10-bit slave address recognition. The first byte of the address will always be acknowledged and the second
byte will raise the address interrupt flag as shown in Figure 27-12.
If the transaction is a write, then the 10-bit address will be followed by N data bytes.