Data Sheet

556
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
27.8.2.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected, Enable-Protected, Write-Synchronized
z Bits 31:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 18 – ACKACT: Acknowledge Action
The Acknowledge Action (ACKACT) bit defines the I
2
C master's acknowledge behavior after a data byte is
received from the I
2
C slave. The acknowledge action is executed when a command is written to CTRLB.CMD, or if
smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
0: Send ACK.
1: Send NACK.
This bit is not enable-protected.
This bit is not write-synchronized.
z Bits 17:16 – CMD[1:0]: Command
Writing the Command bits (CMD) triggers the master operation as defined in Table 27-12. The CMD bits are
strobe bits, and always read as zero. The acknowledge action is only valid in master read mode. In master write
mode, a command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
ACKACT CMD[1:0]
Access R R R R R R/W R/W R/W
Reset00000000
Bit151413121110 9 8
QCEN SMEN
AccessRRRRRRRR/W
Reset00000000
Bit76543210
AccessRRRRRRRR
Reset00000000