Data Sheet

561
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
27.8.2.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: Write-Protected
z Bit 7 – ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
z Bits 6:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 1 – SB: Slave on Bus Interrupt Enable
0: The Slave on Bus interrupt is disabled.
1: The Slave on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Slave on Bus Interrupt Enable bit, which enables the Slave on Bus interrupt.
z Bit 0 – MB: Master on Bus Interrupt Enable
0: The Master on Bus interrupt is disabled.
1: The Master on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus interrupt.
Bit76543210
ERROR
SB MB
AccessR/WRRRRRR/WR/W
Reset00000000