Data Sheet

565
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
FLAG.MB is set. When the corresponding interrupt flag is cleared and the next operation is given, this bit is
automatically cleared.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is not write-synchronized.
z Bit 6 – LOWTOUT: SCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing a one to this bit location will clear STATUS.LOWTOUT. Normal use of the I
2
C interface does not require
the LOWTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the ADDR
register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
z Bits 5:4 – BUSSTATE[1:0]: Bus State
These bits indicate the current I
2
C bus state as defined in Table 27-13. After enabling the SERCOM as an I
2
C
master, the bus state will be unknown.
Table 27-13. Bus State
When the master is disabled, the bus-state is unknown. When in the unknown state, writing 0x1 to BUSSTATE
forces the bus state into the idle state. The bus state cannot be forced into any other state.
Writing STATUS.BUSSTATE to idle will set STATUS.SYNCBUSY.
z Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 2 – RXNACK: Received Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
0: Slave responded with ACK.
1: Slave responded with NACK.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is not write-synchronized.
z Bit 1 – ARBLOST: Arbitration Lost
The Arbitration Lost flag (STATUS.ARBLOST) is set if arbitration is lost while transmitting a high data bit or a
NACK bit, or while issuing a start or repeated start condition on the bus. The Master on Bus interrupt flag (INT-
FLAG.MB) will be set when STATUS.ARBLOST is set.
Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
Value Name Description
0x0 Unknown
The bus state is unknown to the I
2
C master and will wait for a stop condition
to be detected or wait to be forced into an idle state by software
0x1 Idle The bus state is waiting for a transaction to be initialized
0x2 Owner The I
2
C master is the current owner of the bus
0x3 Busy Some other I
2
C master owns the bus