Data Sheet

599
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Writing a one to this bit will clear the Receive Overrun x Interrupt Enable bit, which disables the Receive Overrun x
interrupt.
z Bits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 1:0 – RXRDYx [x=1..0]: Receive Ready x Interrupt Enable
0: The Receive Ready x interrupt is disabled.
1: The Receive Ready x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Ready x Interrupt Enable bit, which disables the Receive Ready x
interrupt.