Data Sheet

664
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
Figure 30-11.Compare Channel Double Buffering
As both the register (PATT/WAVE/PER/CCx) and corresponding buffer register (PATTB/WAVEB/PERB/CCBx) are
available in the I/O register map, the double buffering feature is not mandatory. The double buffering is disabled by
writing a one to CTRLSET.LUPD. This allows initialization and bypassing of the buffer register and the double buffering
feature.
Note: In normal frequency (NFRQ), match frequency (MFRQ) or PWM down-counting counter mode (CTRLBSET.DIR
is one), PER is written at the same time as PERB is written if CTRLB.LUPD is zero or as soon as CTRLB.LUPD
becomes zero.
Changing the Period
The counter period is changed by writing a new value to the Period register or the Period Buffer register. If double
buffering is not used, any update of PER is effective after the synchronization delay.
Figure 30-12.Unbuffered Single-Slope Up-Counting Operation
BV
UPDATE
"APB write enable"
"data write"
=
COUNT
"match"
EN
EN
CCBx
CCx
COUNT
MAX
New value written to
PER that is higher
than current COUNT
Counter Wraparound
New value written to
PER that is lower
than current COUNT
"clear" update
"write"
ZERO