Data Sheet

683
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
z Count during active state of an asynchronous event (increment or decrement, depending on counter
direction). In this case, the counter will be incremented or decremented on each cycle of the prescaled
clock, as long as the event is active.
z Non-recoverable fault
The counter Event Actions are available in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1). For further
details, refer to EVCTRL register description.
Writing a one to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables the
corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that
if several events are connected to the TCC, the enabled action will apply for each the incoming event. Refer to “EVSYS –
Event System” on page 406 for details on how to configure the event system.
30.6.5 Sleep Mode Operation
The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY bit
(CTRLA.RUNSTDBY) must be written to one. The TCC can wake up the device using interrupts from any sleep mode or
performs internal actions through the event system.
30.6.6 Synchronization
Due to the asynchronicity between CLK_TCCx_APB and GCLK_TCCx some registers must be synchronized when
accessed. A register can require:
z Synchronization when written
z Synchronization when read
z Synchronization when written and read
z No synchronization
When a register requiring synchronization is accessed, the corresponding synchronization bit is set in Synchronization
Busy register (SYNCBUSY) and cleared when the synchronization is complete.
An access to a register with synchronization busy bit set, will trigger an hardware interrupt.
The following bits need synchronization when written:
z Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers require synchronization when written:
z Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
z Status register (STATUS)
z Pattern and Pattern Buffer registers (PATT and PATTB)
z Waveform and Waveform Buffer registers (WAVE and WAVEB)
z Count Value register (COUNT)
z Period Value and Period Buffer Value registers (PER and PERB)
z Compare/Capture Value and Compare/Capture Buffer Value registers (CCx and CCBx)
Write-synchronization is denoted by the Write-Synchronized property in the register description.