Data Sheet

689
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181G–SAM-D21_Datasheet–09/2015
This bit is not synchronized.
z Bits 13:12 – PRESCSYNC[1:0]: Prescaler and Counter Synchronization Selection
These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or
on the next prescaled GCLK_TCCx clock. It also makes possible to reset the prescaler on retrigger event, as
shown in the following table.
These bits are not synchronized.
Table 30-6. Prescaler and Counter Synchronization Selection
z Bit 11 – RUNSTDBY: Run in Standby
This bit is used to keep the TCC running in standby mode:
0: The TCC is halted in standby.
1: The TCC continues to run in standby.
This bit is not synchronized.
z Bits 10:8 – PRESCALER[2:0]: Prescaler
These bits select the Counter prescaler factor as shown in the following table.
These bits are not synchronized.
Table 30-7. Prescaler
z Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 6:5 – RESOLUTION[1:0]: Enhanced Resolution
These bits increase the TCC resolution by enabling the dithering options, according to the following table.
These bits are not synchronized.
PRESCSYNC[1:0] Name Description
0x0 GCLK Reload or reset counter on next GCLK
0x1 PRESC Reload or reset counter on next prescaler clock
0x2 RESYNC
Reload or reset counter on next GCLK and reset prescaler
counter
0x3 Reserved
PRESCALER[2:0] Name Description
0x0 DIV1 No division
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV64 Divide by 64
0x6 DIV256 Divide by 256
0x7 DIV1024 Divide by 1024